Why Traditional PCB Methods Fall Short in 3D IC Design
Why are companies rapidly adopting fan-out wafer-level packaging (FO-WLP)—and how does this shift impact the traditional chip design process?
In this episode of the Siemens 3D IC Podcast Series, host John McMillan is joined by Chris Cone, IC Packaging Product Marketing Manager at Siemens EDA, to explore how fan-out wafer-level packaging is transforming advanced semiconductor packaging workflows.
Chris shares his journey from analog design engineer to packaging and automation expert, and breaks down the growing need for intelligent, automated workflows that support the increasing complexity and size of modern designs.
They discuss how new IC packaging techniques demand more automation, design iteration, and cross-functional collaboration than ever before—and why building a replayable, flexible automation language is the key to faster, scalable design success.
Whether you're a layout engineer, SI/PI analyst, or replay coordinator, this episode will show you how to streamline your process using a common design framework and why human-readable automation is the next big leap in fan-out design.
What You’ll Learn in this Episode:
Chris Cone’s journey from analog IC designer to Siemens EDA packaging lead (1:10)
What is fan-out wafer-level packaging, and why is it gaining traction? (1:50)
How FOWLP is different than a traditional BGA design process (2:30)
The four major phases in a fan-out packaging workflow, from tech setup to final verification (3:45)
What is the impact on different roles, such as a package designer, layout designer, engineer, signal integrity, power, and integrity analysis? (8:00)
The three essential traits of successful design automation (10:00)
Key takeaways from real-world projects using Siemens’ automated packaging flows (11:45)
Connect with John McMillan
LinkedIn
Website
Connect with Chris Cone
Website
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13:27
3D IC is Here—But Is Your Architecture Ready for It?
As 3DIC adoption ramps up, it’s becoming clear: microarchitecture needs a rethink. So how do you design hardware that can survive and thrive in the new era of stacked silicon?
In this episode of the Siemens 3D IC Podcast, host John McMillan speaks with Pratyush Kamal, Director of R&D for 3D IC Solutions Engineering at Siemens Digital Industries. With decades of experience spanning Qualcomm and Google, Pratyush brings deep insight into the evolution of IC design—and how 3D integration is transforming every layer of the design stack.
From redefining how and when microarchitecture decisions are made to overcoming the thermal, testing, and failure analysis challenges that come with 3D stacking, this episode dives into the critical topics design teams need to understand today.
You’ll also hear how AI, automation, and cross-disciplinary expertise are reshaping team roles—and why software-defined silicon is redefining the design process itself.
This episode is essential listening for IC architects, system designers, and packaging engineers navigating the transition to advanced 3D IC platforms.
What You’ll Learn in this Episode:
What is microarchitecture in IC design? (2:30)
What does microarchitecture mean in 3D IC design? (3:20)
How early do we need to consider microarchitecture in 3D IC design? (4:45)
The main issues system designers face concerning the increasing complexity of microarchitecture (5:50)
How are roles changing to enable a more holistic outlook on 3D IC microarchitecture? (9:15)
What would enable non-silo design practice? (11:00)
Closing thoughts (11:55)
Connect with John McMillan
LinkedIn
Website
Connect with Pratyush Kamal
LinkedIn
Website
Explore More on 3D IC Innovation & Research:
Deepen your understanding of 3D IC design with these valuable resources:
Home | UCIe Consortium
Die Stacking (3D) Microarchitecture | IEEE Conference Publication | IEEE Xplore
Fine grain 3D integration for microarchitecture design through cube packing exploration | IEEE Conference Publication | IEEE Xplore
Opportunities, Challenges and Mitigations in 3DIC Design, Test, and Analyses | IEEE Conference Publication | IEEE Xplore
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools | IEEE Journals & Magazine | IEEE Xplore
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16:22
The Future of 3D ICs: How Advanced Packaging is Changing the Industry
How are 3D Integrated Circuits (3D ICs) revolutionizing semiconductor design, and what role do advanced packaging technologies play in this transformation?
In this episode of the Siemens EDA Podcast Series on 3D IC chiplet ecosystems , host John McMillan sits down with Jan Vardaman, President and Founder of TechSearch International, to discuss the latest advancements in 3D IC technology, heterogeneous integration, and advanced semiconductor packaging.
Jan shares insights on why 3D ICs are gaining traction, the key industry drivers behind their adoption, and how companies are overcoming integration challenges. She also explores the role of chiplets, AI-driven design processes, and supply chain shifts in shaping the future of semiconductor manufacturing.
Whether you're a semiconductor engineer, a tech enthusiast, or a business leader looking to stay ahead in the industry, this episode is packed with valuable insights into the next generation of IC design.
What You’ll Learn in this Episode:
The main drivers for advanced integration ( heterogeneous or homogeneous silicon) from a technology and business point of view. (02:10)
Specific market segments and industries that are driving these advanced integrations, including chiplet designs ( 3:10 )
The different needs and requirements for packaging ( 6:50 )
How different substrate materials (silicon, RDL, glass core, organic interposer bridges, etc.) compete and complement each other in specific applications ( 8:20 )
Siemens’ Innovator3D IC Platform (10:55)
Connect with John McMillan
LinkedIn
Website
Connect with Jan Vardaman
LinkedIn
Website
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12:00
Uncovering 2.5D and 3D IC Tests
One of the best ways to speed-up product development is to integrate test as early as possible in the design cycle. This shift-left strategy becomes even more critical when advanced IC designs evolve from a single die per package to complex systems with multiple dies integrated into a package. These 2.5D and 3D multi-die design strategies pose some interesting challenges and opportunities for test.
Today, David Lyell interviews Joe Reynick, the Tessent Product Engineering Manager for Siemens EDA. He’ll help us to understand the complexity of development tests for 3D and 2.5D packages.
In this episode, you’ll learn about the challenges of performing comprehensive tests on 3D and 2.5D designs. You’ll also hear about the factors that you need to consider while planning for 3D DFT and IP tests. Additionally, you’ll hear about how 2.5D tests and 3D tests can complement each other.
What You Will Learn In This Episode:
The things you need to be aware of when doing 2.5D and 3D tests (03:34)
The DFT and IP test methods that the DFT and IP test team should implement (09:36)
The die and package level planning interactions needed for 3D DFT and IP test (11:22)
Factors to consider while doing 3D tests (14:20)
What is involved in multi-die IP core test (16:00)
Connect with Joe Reynick:
LinkedIn
Connect with David Lyell:
LinkedIn
Hosted on Acast. See acast.com/privacy for more information.
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21:07
Getting Started with 3D IC
3D IC designs are complex puzzles that engineers have to solve to achieve high performance and reliability. While vertical stacking gives more design options, it also increases the possible number of defective arrangements. There is no one-design-fits-all in 3D IC; engineers must understand their needs and create designs that meet them.
Today, John McMillan interviews John Ferguson, Product Management Director of Calibre DRC Technologies at Siemens Digital EDA. He’ll help us understand the complexity of 3D IC designs and how it impacts their reliability.
In this episode, you’ll learn about some of the guardrails that increase the reliability of 3D IC devices. You’ll also hear about some of the common challenges an engineer has to solve while designing such devices. Additionally, you’ll get some tips on where to start with 3D IC designs to minimize cost and maximize performance.
What You Will Learn in this Episode:
Improving the reliability of heterogeneous assemblies (01:36)
Solving the heat problem in heterogeneous assemblies (07:46)
The sources of mechanical stress in 3D IC assemblies and how to address them (14:44)
Where to start when designing 3D IC devices (22:07)
Connect with John Ferguson:
LinkedIn
Connect with John McMillan:
LinkedIn
Hosted on Acast. See acast.com/privacy for more information.
As the semiconductor industry struggles with the limits of Moore’s Law, traditional monolithic scaling is no longer enough to meet performance, power, area and cost demands in technology, design, analysis, and manufacturing.
3D IC by Siemens is your go-to podcast for exploring the cutting-edge world of 3D IC packaging—a revolutionary approach reshaping semiconductor design, system integration, and heterogeneous computing.
Join industry leaders, engineers, and innovators as we break down advanced IC packaging solutions like 2.5D/3D IC, FCBGA, FOWLP, and more. Discover how chiplets, multi-die integration, and high-bandwidth memory (HBM) are driving higher performance, lower power consumption, and scalable architectures.
In each episode, we dive deep into the challenges and opportunities of IC design and manufacturing, including:
Roadmap for advanced packaging and heterogeneous integration in semiconductor scaling
Mainstream adoption of 3D IC—key challenges and breakthroughs
Optimizing micro-architecture and integration platforms for performance and efficiency
Strategic planning of chiplets and interposers for hierarchical device integration
Leveraging early predictive multi-physics analysis to enhance design accuracy
Automating design and routing for RDL-based fan-out wafer-level packaging (FOWLP)
Exploring glass substrates for superior electrical and thermal performance
Developing test-vehicles and daisy chain designs for architectural validation
Ensuring reliability and manufacturability in 3D IC heterogeneous integration
Mastering Signal Integrity (SI) and Power Integrity (PI) Analysis for high-speed systems
Managing thermal challenges in stacked die architectures
Subscribe now and stay ahead in the world of 3D IC.
Learn more: Siemens 3D IC Packaging Solutions
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