The EEcosystem Podcast

If you tried AI 2-3 years ago with unsophisticated, error-prone LLMs, Collin Stoner says it’s time to look again. In this episode, Judy Warner talks with Collin, an electrical engineer and co-founder of Zenode.ai, about the shift from one-shot answers to agents that can search, use tools, and work in parallel. Collin shows how that change is reshaping an engineer’s day: agents can surface details buried deep in datasheets and compare hundreds of components, while the engineer spends more time innovating, testing ideas, weighing tradeoffs, and making design decisions. They also openly discuss where AI still falls short, why engineering judgment matters, and how newer engineers can use these tools to learn rather than skip the learning.

Zenode Website: https://zenode.ai/

Join The Engineering EEcosystem for more engineering free content, more resources and free online Masterclasses with Dr. Eric Bogatin https://theeecosystem.com

 

0:00 Introduction to AI in engineering

0:53 Understanding Zenode

3:28 The evolution of AI tools

7:40 Defining the role of engineering judgment

13:21 Practical power supply use case 23:10 Optimizing research workflows

27:43 Addressing AI skepticism

34:20 Learning and future outlook

AI is already transforming hardware engineering. In this episode, Judy Warner and AllSpice.io co-founder and CEO Valentina Ratner explore where AI belongs in the workflow and where it doesn’t. They discuss AI-assisted design reviews, deterministic automation, agent-to-agent workflows, trustworthy data, measurable ROI, and why engineering judgment and final approval must remain firmly in human hands.
 
About the guest: Valentina Ratner is the co-founder and CEO of AllSpice.io. An engineer by background, she co-founded AllSpice.io to reduce the repetitive, manual work surrounding electronics development and give engineering teams more time for design, discovery, and high-value decision-making.
 
00:00 The unknown unknowns AI can catch
00:38 Meet Valentina Ratner and AllSpice.io
03:48 Three buckets: AI, automation, and humans
06:40 Where AI delivers real engineering value
12:41 How DRCY "Darcy" checks accuracy and blind spots
15:31 Connecting a diverse engineering tool stack
20:39 Headless workflows and agents talking to agents
24:29 Measuring ROI, time savings, and avoided respins
30:17 Why hardware AI is no longer a question of if
35:22 How to future-proof the engineering stack
40:18 What is next for DRCY and AllSpice
 
Learn more about AllSpice: https://allspice.io
Subscribe to The Engineering EEcosystem Podcast for more conversations about the tools, technologies, and people shaping electronics engineering.
 
Free online Electronics design Masterclasses with Eric Bogatin at https://theeecosystem.com/masterclass
 
Sponsor Links
 
💡For SI/PI/EMI News and Technical Resources, and to register for a free subscription, visit the Signal Integrity Journal today. https://www.signalintegrityjournal.com/
 
Quilter AI-assisted PCB Design Layout: https://www.quilter.ai/
 
Siemens EDA, Free demo of Xpedition Standard for EEcosystem Members: https://tinyurl.com/Siemens-Xpedition...
 
Keysight EDA https://www.keysight.com/in/en/produc...

In this episode, Judy Warner talks with Roberto Piacentini, an electrical engineer with 30+ years of experience and now Director of Global Marketing for Design Engineering Software at Keysight Technologies, about what he considers the most expensive engineering mistake, why growing design complexity is raising the stakes, and how to avoid these costly issues.

They explore connected workflows, engineering silos, simulation, data, and AI-augmented tools (keeping engineers in control and putting AI in the human loop, and how these technologies can help engineers make better decisions across the design lifecycle.

What You'll Learn

-Where engineering silos create risk

-How connected workflows help

-Why good engineering data matters for AI

-AI-augmented vs. AI-driven engineering

-How simulation can reduce costly physical iterations

 

Attend Keysight Design Forum: August 26, 2026 Huntsville, AL

Learn More and Register: https://tinyurl.com/4hd8d63a

 

Attend Keysight Design Forum: September 24, 2026, Santa Clara, CA

Learn More and Register: https://tinyurl.com/yrvb4e4k

AI is everywhere in the headlines right now, but is it actually doing anything positive for engineers? Or is it just going to take jobs and produce less competent engineers by putting everything on autopilot? I sat down with Tobias Pohl, Co-Founder and CEO of CELUS, and Matt Bromley, VP of Product Strategy for Siemens EDA, to try to get past the hype and talk honestly about what agentic AI is actually changing, from early concept and ideation all the way through the PCB design process, and just as importantly, what it's not changing.

CELUS and Siemens EDA have partnered to bridge that early, "fuzzy" stage of concept design into the traditional schematic, layout, and manufacturing flow. Toby and Matt talk about how agentic AI is compressing the design flow, from comparing datasheets and selecting components to running simulations, while the architecture and the judgment calls stay firmly with the engineer. They also talk about how agentic AI is now working across toolsets. Engineers can ask a question in one platform and have it orchestrated across another, without all the manual handoffs, file conversions, and integration work that used to eat up so much time and introduce design risks. 

 

00:00 — Introductions Toby and Matt introduce themselves and how the CELUS/Siemens EDA partnership came together.

01:17 — Why CELUS and Siemens EDA partnered The gap between early concept design and traditional engineering tool chains, and how the two platforms connect ideation to schematic, layout, and manufacturing.

04:20 — The real bottlenecks in modern design Why comparing datasheets and chip selection can eat weeks of engineering time, and how a non-linear design process creates constant rework.

07:59 — Where AI is already delivering real value Extracting models and data from datasheets, evaluating BOM choices against manufacturability and lead time, and using AI to interpret simulation results.

11:35 — Inside agentic architecture Toby explains the shift from single LLM assistants to full agentic systems, including guardrail agents, review agents, and orchestration across multiple tools, including agents that hand off work between CELUS and Siemens EDA without the engineer manually reconnecting the two.

17:54 — Does the engineer stay in control? I push Toby and Matt directly on whether AI is encroaching on architecture and design judgment. The answer is still no, and they explain why.

19:39 — Walking the design journey, start to finish Toby and Matt trace a real workflow: describing design intent in natural language, generating an initial architecture, comparing multiple approaches, and handing off an electrically correct design into Siemens EDA tools for simulation, layout, and DFM.

28:19 — Who holds the judgment Why the designer still drives architecture and intent, and how agentic tools add robustness rather than replace decision-making.

35:00 — The hard question about jobs I ask the question our listeners won't forgive me for skipping: didn't software engineers lose jobs when AI hit? Toby and Matt respond with the historical parallel to compilers, high-level languages, and past technology hype cycles.

40:46 — What's next Toby and Matt preview upcoming agentic capabilities across both platforms and how you can start exploring the tools yourself.

Key takeaway
The engineer remains the design intent and architecture. Agentic AI is built to take the manual grind out of design, the spreadsheets, the datasheet comparisons, the repetitive tool-switching, so engineers can spend more of their time on the judgment calls, the creativity, and the innovation that only they can bring.

Learn more
Siemens EDA: 

To learn more about Xpedition and PCB Design

For a 30-day trial of Xpedition Standard with powered-by-CELUS integration

Matt Bromley on LinkedIn

 

CELUS: 

CELUS Website

CELUS Platform

Tobias Pohl on LinkedIn

As AI, data centers, aerospace, and advanced computing continue pushing bandwidth and power requirements to new extremes, DDR memory compliance has become one of the biggest bottlenecks in high-speed digital design. I

n this episode, Judy Warner is joined by Ben Dannan, Founder of Signal Edge Solutions, and Tyler Huddleston, SI/PI Engineer of SES, to explore why traditional DDR compliance workflows can consume days or weeks of engineering time, produce false positives, and slow product development.

They also demonstrate how their new software, Mem Check Pro, automates JEDEC compliance analysis, including setup/hold, crossing points, slew rate, and commonly skipped checks like clock monotonicity and VIX, in just a few minutes. This helps engineering teams verify designs faster and with greater accuracy and confidence.

Learn more at https://Signaledgesolutions.com

Join The Engineering EEcosystem for free resources for professional engineers, including our FREE online SI Masterclasses by Dr Eric Bogatin. https://theeecosystem.com